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SI9990ACS vishay siliconix faxback 408-970-5600, request 70655 s-60752rev. c, 05-apr-99 www.siliconix.com 1 5-v vcm driver/spindle motor driver for 1.8- and 2.5-hard disk drives description the SI9990ACS has a 3-phase brushless dc (spindle) motor driver and a linear transconductance amplifier suitable for driving a voice coil motor (head actuator). spindle motor driver the spindle driver features three 1-a, 2.3- w (total) all n-channel mosfet half-bridge output stages. the spindle driver uses internal back emf sensing circuitry that eliminates the need for hall sensors. an internal charge pump allows rail-to-rail output voltage swing with a nominal 5-v supply. a unique output structure eliminates the need for an external schottky diode to isolate the system 5-v supply if it fails during operation. this makes the output half-bridge drive capability equivalent to drivers with 1-a, 1.9- w specifications in series with the required schottky diode. vcm driver the vcm driver provides all necessary functions including a motor current sense amplifier, a loop compensation amplifier and a 300-ma power amplifier featuring four mosfets in an h-bridge configuration. the output crossover protection ensures no cross-conducting current and class ab operation during linear tracking. externally programmable gain switching at the input summing junction increases the resolution and dynamic range for a given dac. the head retract circuitry can be activated by either an undervoltage condition or an external command. an external resistor is required to set the vcm current during retract. the retract voltage clamp is set at 0.44 v. a reference generator and two uncommitted amplifiers are also provided for analog interface. in sleep mode, internal logic initiates a head retract operation followed by spindle brake and shutdown of all analog circuitry except the supply monitor. the standby power dissipation is less than 6 mw. the vcm may also be disabled without disabling spindle operation (idle mode). all controls from the microprocessor are communicated via the serial interface. additional housekeeping functions of the driver include thermal shutdown and undervoltage lockout. the SI9990ACS is manufactured using a self-isolated bic/ dmos process and is available in a 64-pin sqfp package for operation over the commercial (0 to 70 c) temperature range. features benefits applications ? on-board half-bridge drivers C spindle = 2.3 w total at 1 a Cvcm = 3.3 w total at 0.3 a ? spindle driver features: C back emf commutation C linear current control C internal current sense resistor C start-up current limit (10% accurate) ? single 5-v supply ? rail-to-rail output voltage swing ? vcm driver features: C class ab linear operation C externally programmable gain and bandwidth C programmable retract current and fixed voltage clamp ? over-temperature protection ? system voltage monitor ? undervoltage head retract ? sleep mode and idle mode ? reference generator ? two uncommitted amplifiers si9990a
SI9990ACS vishay siliconix s-60752rev. c, 05-apr-99 faxback 408-970-5600, request 70655 2 www.siliconix.com functional block diagram
SI9990ACS vishay siliconix faxback 408-970-5600, request 70655 s-60752rev. c, 05-apr-99 www.siliconix.com 3 absolute maximum ratings voltages referenced to common pin v dd supply range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 v to 7 v pin (output a, b and c) . . . . . . . . . . . . . . . . -0.3 v to v clamp + 0.3 v pin (output + and -) . . . . . . . . . . . . . . . . . . . . . . -0.3 to v mot + 0.3 v pin (chs, cp1h, cp2h) . . . . . . . . . . . . . . . . . . . . . . . .-0.3 v to 16 v maximum output current a output a, b and c (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 a output a, b, and c (continuous) . . . . . . . . . . . . . . . . . . . . . . 0.4 a output + and - (peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 a output + and - (continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 a pin (all others) . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 v to v dd + 0.3 v maximum clamp current b output a, b and c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 a output + and -. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 a (pulsed 10 ms at 10% duty cycle) all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma v mot to v clamp diode (peak) . . . . . . . . . . . . . . . . . . . . . . .100 ma v mot to v clamp diode (continuous) . . . . . . . . . . . . . . . . . . .50 ma v mot to chs diode (peak) . . . . . . . . . . . . . . . . . . . . . . . . . .50 ma v mot to chs diode (continuous) . . . . . . . . . . . . . . . . . . . . .25 ma storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150 c operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c power dissipation c 64-pin sqfp . . . . . . . . . . . . . . . . . . . . . 2.0 w thermal impedance ( q ja ) c 64-pin sqfp . . . . . . . . . . . . 62.5 c/w notes a. output current rating is dependent on the system duty cycle, start- up timing and heat dissipation capability. b. diode currents depend on power supply start-up transient and bypass capacitor values. c. device mounted with all leads soldered or welded to pc board. specifications parameters symbol test conditions unless specified v adin = v dd = v mot = 5 v 10% r s (vcm) = 1.67 w r spin = 17 k w , t a = 0 to 70 c limits unit min typ max supply supply current i dd + i mot static, no load, sleep mode 0.9 1.2 ma static, no load, normal operation 20 41 static, no load, idle mode 14 19 v dd , v mot operating range v dd , v mot 4.5 5 5.5 v control logic low input voltage (g/s, data, clk, cs , p u , p d ) v il -0.3 1.5 v high input voltage v ih 3.5 5.3 low input current i il v in = 0 v -1 a high input current i ih v ih = 5 v 1 mode pin pull down current i pd v in = 5 v 100 low output voltage (f com , fault , p out )v ol i out = 500 a 0.5 v high output voltage v oh i out = -500 a 4 p out off-state leakage current v out = 2.5 v -1 1 a emf comparator offset v os 20 40 70 mv maximum emf comparator input common mode voltage 4.3 v cst current i cst charging or discharging 5 a cd current (cd1 or cd2) i cst1 or i cst2 charging 10 discharging -20 i cd (discharging)/i cd (charging) c d1 or c d2 2.0 cwd current i cwd charging 5 a discharging -25 cwd threshold voltage v tl 0.5 v v th 2.50
SI9990ACS vishay siliconix s-60752rev. c, 05-apr-99 faxback 408-970-5600, request 70655 4 www.siliconix.com spindle transconductance amplifier (a 1 ) voltage gain a v r load = 50 k w to v r (see note a) measured at 1.2 to 2.9 v 60 db gain-bandwidth f o r load = 50 k w , c load = 100 pf to v r 1mhz slew rate sr 0.5 v/s output voltage swing v out r load = 50 k w to v r bits d 2 d 3 = 00 to 11 0.8 3.1 v input bias current i b 50 na offset voltage v os 10 mv power supply psrr f = 10 khz 50 db spindle transconductance amplifier (a 6 and a 7 ) transconductance g ms r load = 4 w to v mot 0.4 0.5 0.6 a/v output current limit accuracy -20 20 % -3 db bandwidth f o r load = 4 w to v mot , c load = 100 pf 70 khz slew rate sr 1 v/s output current cutoff voltage measured at oa1 with respect to gnd 2.70 2.85 3.0 v spindle half-bridge on-resistance (sink or source) r ds(on) i out = 1 a 0.6 w i out = 1 a including 0.23 w r s 0.7 (sink + source), i out = 1 a 2.3 output leakage current i ds(off) v out = v mot 100 a v out = 0 v -100 clamp diode v f(on) i out = 1 a -1.5 v vcm transconductance amplifier (a 3 , a 4 , a 5 , a 9 , a 10 and dmos fets) transconductance g mvh gain select = high, i out = 300 ma 142 150 158 ma/v g mvl gain select = low, i out = 75 ma 35.6 37.5 39.4 output offset current, high gain i os , hg gain select = high -5 0 +5 ma output offset current, low gain i os , lg i os (g/sel = high)-i os (g/sel = low) -5 0 +5 output compliance v oh i oh = 0.3 a, v mot = 4.5 v, output 3.9 4.2 v v ol i ol = 0.3 a, v mot = 4.5 v, output 0.2 0.4 clamp diode voltage v cl i f = 0.3 a 1.5 feedback resistance r f from i sense(out) to ia4 10 k w 3 db bandwidth a 4 , a 5 1 mhz a 9 , a 10 0.4 psrr @ 10 khz 50 db output swing a 3 , a 5 r load = 50 k w to v r 0.2 v dd -0.2 v a 4 1.2 v dd -1.2 reference generator (a 8 ) input resistance measured at v adin pin 72 k w output voltage v r i out = 2 ma 2.37 2.5 2.63 v specifications parameters symbol test conditions unless specified v adin = v dd = v mot = 5 v 10% r s (vcm) = 1.67 w r spin = 17 k w , t a = 0 to 70 c limits unit min typ max
SI9990ACS vishay siliconix faxback 408-970-5600, request 70655 s-60752rev. c, 05-apr-99 www.siliconix.com 5 notes a. 50-k w load is in addition to the r spin load. power supply monitor v dd undervoltage threshold 3.7 3.9 4.1 v hysteresis 70 mv overtemperature protection trip point 165 c hystersis 20 head retract function (undervoltage or sleep mode; c dly tied to v clamp ) i ret bias voltage v ret 0.25 v retract output current limit i out+ r ret = 2.5 k w , v out+ = 0.2 v 14 20 26 ma retract output voltage limit v out- i out- = -20 ma 0.31 0.44 0.5 v emergency retract supply current i clamp v clamp = 3 v, r ret = 2.5 k w v dd = 0 v, static, no load 24ma retract supply voltage range v clamp 1.41 5 5.5 v chs leakage i chs v dd = 0 v, v clamp = 3 v, v chs = 10 v 2 a dc to dc converter (charge pump) output voltage chs i chs = -5 ma, v dd = v mot = 4.5 v 11 v flyback clamp flyback clamp switch resistance normal mode, i clamp = 0.1 a 4 w clamp zener voltage v z i clamp = 0.1 a 9.1 v uncommitted amplifier (a 2 ) input offset voltage v os -15 0 +15 mv input bias current i b 50 na unity gain bandwidth r load = 50 k w , c load = 100 pf to v r 1mhz slew rate sr 1 v/s power supply rejection ratio psrr @ 10 khz 50 db open loop voltage gain a vol r load = 50 k w to v r , measured at v r 1.8 v 60 output voltage swing v o r load = 50 k w to v r 0.2 v dd - 0.2 v timing chip select to clock setup time t cs see timing diagram, figure 1. 160 ns data setup time t ds 160 data hold time t dh 160 head retract time-out (brake delay) t dly t dly = 514 k w x c dly , c dly = 0.18 f, v dd = 0 v, v clamp = 1.41 to 5.5 v 55 100 240 ms specifications parameters symbol test conditions unless specified v adin = v dd = v mot = 5 v 10% r s (vcm) = 1.67 w r spin = 17 k w , t a = 0 to 70 c limits unit min typ max i ret v ret r ret --------------- , i out 200 i ret () C = =
SI9990ACS vishay siliconix s-60752rev. c, 05-apr-99 faxback 408-970-5600, request 70655 6 www.siliconix.com detailed description serial port a 6-bit word at the serial port data pin is used to program basic operating conditions. the function of each bit is shown in tables 1 and 2. to write data to the serial port, cs is pulled low during clock low. this holds the existing word while new data is written into the shift registers on a positive clock edge. the new data becomes valid on the rising edge of cs . when cs is high, clock is disabled and data cannot be shifted. d0 is the last bit written to the serial port. it enters sleep mode (d0 = 0) upon power up. when d0 is written 0, a head retract is automatically initiated and t dly applies following the next cs rising edge. the mode pin is used for production testing only. it should be tied low during normal operation. table 1. serial port definitions table 2. spindle current limit g ms = transconductance (refer to vcm design equations) figure 1. write cycle timing diagram bit name function 01 d0 sleep mode/system enable sleep mode: vcm retracted, spindle and vcm brake applied after period t dly normal operation d1 spindle brake normal operation spindle disabled and brake applied, vcm enabled d2 spindle current limit see table 2. d3 spindle current limit see table 2. d4 idle mode/vcm enable idle: vcm disabled and brake applied, spindle running normal operation d5 spindle step mode normal operation test pin becomes single step commutation clock d2 d3 current limit current limit (r spin = 17 k w ) current limit (r spin = 15.7 k w ) 0 0 1.85 v ? g ms 925 ma 1 a 0 1 1.45 v ? g ms 725 ma 780 ma 1 0 1.05 v ? g ms 525 ma 570 ma 1 1 0.65 v ? g ms 325 ma 350 ma
SI9990ACS vishay siliconix faxback 408-970-5600, request 70655 s-60752rev. c, 05-apr-99 www.siliconix.com 7 motor shutdown sequence the SI9990ACS executes a motor shutdown sequence whenever v dd drops below 3.9 v (emergency retract), or serial bit d0 is set low (sleep mode). the shutdown sequence is terminated by a programmable one-shot (brake delay). during the time-out (t dly ), both the spindle and vcm outputs are turned off. simultaneously, a separate vcm retract circuit is activated. as shown in figure 2, the all-bipolar design enables retract function all the way down to a supply of 1.41 v at v clamp pin. the retract current typically is 20 ma, adjustable with an external resistor, r ret . to limit retract velocity, a fixed clamp limits the voltage across vcm to no more than 440 mv. after the time-out, the retract circuitry is shut off while the spindle motor and vcm brake is activated by turning on all low-side dmos drivers. to brake faster (i.e., with lower impedance short across the motor windings) the low-side drivers are powered by the residual charges on the chs bypass capacitor. figure 2. simplified retract circuit spindle driver table 3. spindle pwm speed control (double integrator) table 4. spindle commutation sequence note: x = dont care, z = high impedance system state p u p d p out state run 0 0 1 decel run 0 1 z hold run 1 0 z hold run 1 1 0 accel spindle brake/ sleep xx0accel sequencer state out a out b out c reset * zzz 1highlowz 2highzlow 3 z high low 4 low high z 5 low z high 6 z low high *reset is the state after exiting sleep or spindle brake mode.
SI9990ACS vishay siliconix s-60752rev. c, 05-apr-99 faxback 408-970-5600, request 70655 8 www.siliconix.com pin description power supplies function pin number description v dd 61 +5-v supply for vcm and spindle controller logic. v mot 7, 8, 57, 58 +5-v supply for vcm and spindle drivers. v clamp 53 inductive flyback clamp and emergency head retract power supply. this pin is shorted to v mot by an on-chip switch during normal operation. the switch eliminates the need for an external schottky diode. agnd 24 low noise ground return for critical analog functions gnd 3, 4, 11, 12, 36, 37, 38, 39, 42, 43 ground return for the entire chip. all ground pins are connected to each other through the die substrate and lead frame. the large number of direct connections to the lead frame lowers thermal impedance and improves power dissipation. chs 56 output of the dc-todc converter, used to power vcm and spindle drive mosfets. the converter is a 3x charge pump capable of sourcing 5 ma. an external >0.1 f capacitor between pin 56 and ground is necessary. cp2h 59 positive side of the external 3x charge pump capacitor. cp1h 60 positive side of the external 2x charge pump capacitor. cp2 54 500-khz oscillator output, used to drive the 3x charge pump. cp1 55 inverted output of the on-chip 500-khz oscillator, used to drive the external 2x charge pump capacitor. v adin 23 low noise +5-v supply pin for the on-chip reference generator. v r 22 output of the on-chip reference generator: v r = v adin /2. this is used as the dc reference level for all analog signals. voice coil motor driver function pin number description gain select 2 input pin used to select vcm transconductance. a high input sets the gain to the maximum and a low input sets the gain to be 1 / 4 of the maximum. v dac 16 inverting input of servo pwm filter amplifier. oa3 15 output of servo pwm filter amplifier. connect r c network from this pin to v dac to set filter bandwidth. a positive oa3 relative to v r will set v cm output current positive. ia4 14 inverting input of v cm loop compensation amplifier. oa4 13 output of v cm loop compensation amplifier. connect lead-lag network from this pin to ia4 to set desired loop bandwidth. i sense in+ 62 positive input terminal for v cm current sense amplifier. this pin connects to external sense resistor and v cm . i sense in- 63 negative input terminal for v cm current sense amplifier. this pin connects to the other side of sense resistor and out+ pin. i sense out 64 output terminal of v cm current sense amplifier. out+ 5, 6 v cm power amplifier positive output terminal. current from out+ is positive. out- 9, 10 v cm power amplifier negative output terminal. during head retract, v cm output current will be negative, or flowing from this pin into the v cm load. i ret 1 control pin for head retract current (nominally 0.25 v). an external resistor is connected to this pin. the current is amplified 200 times at the v cm driver. c dly 21 an external capacitor is connected to this pin to set the maximum head retract time, t dly = 514 k w x c dly . at the end of the delay, the spindle motor is set to brake. a head retract may also be forced, by asserting this pin low.
SI9990ACS vishay siliconix faxback 408-970-5600, request 70655 s-60752rev. c, 05-apr-99 www.siliconix.com 9 microcontroller interface function pin number description data 18 data input for the serial port. clk 19 clock input for serial port data. cs 20 strobe input for data word. system commands are executed at the rising edge of cs . fault 17 undervoltage flag output. forced low if 5-v supply drops below 3.9 v, or the internal power-on reset timer (approximately 0.5 ms) is timing out. diagnostic functions function pin number description mode 51 control input used for manufacture testing only. grounded or left open during normal operation. test 52 used as temperature test or step mode clock input. controlled by serial port. spindle motor driver function pin number description f com 27 spindle commutation clock output. a positive going pulse is generated whenever a valid back emf zero crossing is detected. the external speed control, working in either phase or frequency domain, compares this signal against a reference clock and feedbacks a pwm servo signal to the spindle driver via the pwm decoder and low-pass filter (a 2 ). p u 49 pulse width modulation pull-up command from speed control. p d 50 pulse width modulation pull-down command from speed control. p out 48 pulse width modulation output from speed control. this pin is connected to the external integrating resistor of a 2 . p out is low, or accelerating, if p u = high and p d = high. p out is high, or decelerating, if p u = low and p d = low. p out is tri-state, or holding, otherwise. ia2 25 inverting input of spindle pwm low-pass filter amplifier. oa2 26 output of spindle pwm low-pass filter amplifier. connect rc network from this pin to ia2 to set desired cutoff frequency. ia1 35 inverting input of spindle loop compensation amplifier. oa1 34 output of spindle loop compensation amplifier. connect rc lead-lag network from this pin to ia1 to set compensation. r spin 33 connect an accurate external resistor from this pin to oa1 to set spindle transconductance and current limit. the recommended resistance is 17 k w . out a 46, 47 spindle phase a output terminal. out b 44, 45 spindle phase b output terminal. out c 40, 41 spindle phase c output terminal. cst 31 an external capacitor connected to this pin will generate commutation pulses to start up the spindle motor. cwd 30 an external capacitor connected to this pin will disable the back emf comparators during diode recirculation, detect incorrect motor rotation or stall. cd1 29 connect at this pin one of the two external capacitors used to generate the ideal commutation point from the back emf zero crossing points. cd2 28 connect a second capacitor identical to cd1 at this pin to generate the optimum commutation delay. ct 32 spindle motor center tap input for back emf sensing.
SI9990ACS vishay siliconix s-60752rev. c, 05-apr-99 faxback 408-970-5600, request 70655 10 www.siliconix.com application 64-pin sqfp test board for typical 2?" or smaller hdd (shown with external phase detector for spindle speed control and external pwm for vcm dac) vcm design equations: (1) transconductance (g mv ) (2) output retract current spindle design equation: (3) transconductance loop compensation (4) refer to an93-1 for all servo equations. high gain 1 4r s ------------- ; g/sel = high = low gain 1 16 r s --------------- - ; g/sel = low = i out 200 i ret 200 0.25 v r ret ---------------- - == transconductance g ms () 8700 r spin --------------- - = closed-loop bw 416 () 2 p 10 k () c l ----------------------------------- = r s r m r s + --------------------- - ? ?? c l 64 2 p 10 k () bw -------------------------------------- = r l l m c l r m r s + () ---------------------------------- = r s r m r s + --------------------- - ? ?? or r m motor resistance = l m motor inductance =
SI9990ACS vishay siliconix faxback 408-970-5600, request 70655 s-60752rev. c, 05-apr-99 www.siliconix.com 11 application table 5. components for test board package outline: sqfp 64-pin name value comments r1 100 k vcm pwm low pass filter r2 100 k vcm pwm low pass filter r3 100 k vcm pwm low pass filter r4 2.61 k vcm transconductance amplifier compensator r6 39 k spindle pwm low pass filter r7 110 k spindle pwm low pass filter r8 5.6 m spindle speed control lead-lag compensator r9 910 k spindle speed control lead-lag compensator r10 470 k spindle speed control lead-lag compensator r11 17 k r spin resistor r12 1.67 vcm sense resistor r13 2.5 k vcm retract bias resistor (r ret ) r14 30 vcm snubber resistor r15 30 vcm snubber resistor r16 62 spindle snubber resistor r17 62 spindle snubber resistor r18 62 spindle snubber resistor c1 1.2 nf vcm pwm low pass filter c2 100 pf vcm pwm low pass filter c3 18 nf vcm transconductance amplifier compensator name value comments c4 27 nf spindle start-up capacitor c5 680 pf spindle watch-dog capacitor c6 1.8 nf spindle commutation delay capacitor #1 c7 1.8 nf spindle commutation delay capacitor #2 c8 0.22 nf spindle loop zero capacitor c9 2.7 nf spindle pwm low pass filter c10 2.2 nf spindle speed control lead-lag compensator c11 10 nf spindle speed control lead-lag compensator c12 82 nf charge pump capacitor #1 c13 82 nf charge pump capacitor #2 c14 100 nf vcm snubber capacitor c15 100 nf vcm snubber capacitor c16 180 nf spindle snubber capacitor c17 180 nf spindle snubber capacitor c18 180 nf spindle snubber capacitor c19 3 0.1 f bypass capacitor c20 3 0.1 f bypass capacitor c21 3 0.1 f bypass capacitor c22 180 nf brake delay capacitor (c dly ) note: these values are entirely dependent on motor characteristics. *for reference only dim millimeters inches* min max min max a 1.35 1.60 0.053 0.063 a 1 0.04 0.16 0.002 0.006 b 0.14 0.26 0.006 0.010 c 0.117 0.177 0.005 0.007 d 9.90 10.10 0.390 0.398 d 1 11.7 12.3 0.461 0.484 e 0.40 0.60 0.016 0.024 l - 10.80 - 0.425 l 1 10.80 11.20 0.425 0.441 l 2 0.30 0.70 0.012 0.028 s - 1.20 - 0.047 q 0 4 0 4

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